The present invention relates to thin film transistors, and more particularly to a method for fabricating a vertical thin film transistor capable of improving a current driving capability.
General, thin film transistors may be used in SRAM devices of 1M grade or above in place of load resistors. Also, such thin film transistors are widely used as switching devices for switching a picture data signal in each pixel region of liquid crystal displays (LCDs) and for sequentially switching photo charges generated in each photodiode of contact image sensors.
In such thin film transistors used as switching devices in integrated LCDs or contact image sensors, an accurate and rapid switching function can be achieved in so far as no leakage current is generated between a source and a drain and a parasitic capacitance present between a gate and the source/drain is maintained in a small level.
FIGS. 1a to 1c are sectional views respectively illustrating a method for fabricating a conventional vertical thin film transistor. FIG. 2 is a sectional view explaining an operation of the vertical thin film transistor fabricated in accordance with the method of FIGS. 1a to 1c. On the other hand. FIG. 3 is a graph illustrating a voltage-current variation between a source and a drain in the vertical thin film transistor of FIG. 2 depending on a gate voltage.
In accordance with the conventional method, a gate electrode 2 is formed over a glass substrate 1, as shown in FIG. 1a. Over the gate electrode 2, a gate insulating film 3, a first intrinsic amorphous silicon (i-a-Si:H) layer 4 and a high concert%ration n (n.sup.+) type doped amorphous silicon (n.sup.+ a-Si:H) layer 5 and a metal electrode 6 for an ohmic contact are sequentially formed, in this order.
As shown in FIG. 1b, the metal electrode 6 and the high concentration n type doped amorphous silicon 5 is selectively removed to form source electrodes 6a.
Subsequently, a second intrinsic amorphous silicon (i-a-Si:H) layer 4a to be used as an active layer is deposited to a thickness of several ten hundreds angstroms over the entire exposed surface of the resulting structure, as shown in FIG. 1c. Over the second intrinsic amorphous silicon layer 4a, a high concentration n type doped amorphous silicon layer 7 for an ohmic contact and a metal electrode 8 to be used as a drain electrode are sequentially deposited. Thus a vertical thin film transistor is fabricated.
The conventional vertical thin film transistor has a structure in which the gate electrode 2 is disposed at the lower portion of the structure while the source electrode 6a and the drain electrode 8 are disposed above the gate electrode 2.
Operation of the conventional vertical thin film transistor having the abovementioned structure will now be described.
In FIG. 2, the upper surface of the source electrode 6a has a Schottky contact characteristic whereas the lower surface of the source electrode 6a is in contact with the high concentration n type doped amorphous silicon layer 5a and thus has an ohmic contact characteristic. Accordingly, when a voltage is applied to the gate electrode 2, a channel is formed in the first intrinsic amorphous silicon layer 4 disposed beneath the source electrode 6a by virtue of an electric field generated by the applied voltage. As a voltage is applied to the source electrode 6a, current flows from the lower surface of the source electrode to the drain electrode 8.
FIG. 3 is a graph illustrating a variation in current flowing through the source and drain depending on the voltage applied to the gate electrode 2. As shown in FIG. 3, when the voltage applied to the gate electrode 2 has a higher level, the amount of current flowing between the source and drain is increased. As the voltage between the source and drain becomes higher, the amount of current flowing between the source and drain is also increased.
However, the conventional vertical thin film transistor has the following problems.
First, the gate electrode 2 can not control the channel in one direction. Although a Schottky contact characteristic is provided between the source electrode 6a and the intrinsic amorphous silicon layer disposed over the source electrode 6a, it is weak. As a result, a leakage current may flow between the source and drain when the voltage difference between the source and drain is high. Due to such a leakage current, the thin film transistor has a degraded reliability.
Second, the fabrication is complex because two intrinsic amorphous silicon layers as active layer are formed. Such a complex fabrication results in a long fabrication time and thereby a reduced productivity.
Third, the characteristic of the thin film transistor is degraded because a parasitic capacitance is present between the source and drain.